This console also features a special ‘anomaly’ called Open Bus: If there is an instruction trying to read from an unmapped/invalid address, the last value read is supplied instead (the CPU stores this value in a register called Memory Data Register or MDR). The system provides eight channels to set up DMA transfers, thus enabling to dispatch up to eight independent transfers at once. This avoids interrupting the CPU for long intervals but transfers are limited to 4 bytes per scan-line.
Horizontal DMA (HDMA): Performs a small transfer after each horizontal scan (while the CRT beam is preparing to draw the next row).General Purpose DMA: Performs transfers at any time, bear in mind that the CPU is stopped until the transfer is finished.There are two DMAs to choose from depending on the needs : When a DMA is being set up, the origin must come from a different bus than the destination. 8-bit ‘B Bus’ controlled by the S-PPU: Connects the cartridge, CPU, WRAM, S-PPU and the Audio CPU.24-bit ‘A Bus’ controlled by the CPU: Connects the cartridge, CPU and WRAM.8-bit external data bus: Meaning that it takes twice the cycles to move its 16-bit registers across external memory!Īpart from the extra registers, Ricoh customised the core design to include two exclusive DMAs (Direct Memory Access) that enable to move data around without the intervention of the CPU (resulting in faster speeds).įor this design to work, regions of memory are referenced using two different address buses :.New 16-bit multiplication and division units added by Ricoh, which provide the CPU with the ability to carry out these types of operations by hardware (the 65C816 doesn’t include any dedicated instructions for multiplication or division).Furthermore, the accumulator (where arithmetic operations are performed) and index register (used to compute memory addresses) can switch between 16-bit and 8-bit modes. A 65816 ISA: A 16-bit instruction set which extends the original 6502 ISA, but doesn’t implement undocumented instructions some NES games resorted to use.The CPU employs a variable clock speed that will reach up to 3.58 MHz during register operations and down to 1.79 MHz when accessing slow external buses (i.e. the serial/controller port). Since the SNES shares the same foundation as the NES’ CPU, there’s a slight possibility that the SNES was originally planned to be compatible with NES games.
SUPER NINTENDO SERIAL NUMBER 001 UPGRADE
It’s based on the Western 65C816, a 16-bit upgrade of the classic MOS Technology 6502. Consequently, the Super Nintendo was designed with expandability in mind: In a world where CPUs are evolving faster than the speed of light, Nintendo depended on game cartridges to make its console shine. Nintendo managed to bring the next generation of graphics and sounds without using expensive off-the-shelf components. Motherboard with important parts labelled Diagram Main architecture diagramīus 'A' and 'B' are address buses, the data bus follows the trail of bus 'B' and it's 8 bits wide. Earlier revisions had the Sound Subsystem connected as a daughterboard, later ones unified both PPUs.
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